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安全芯片规格
32-bits Andes SN801 Secure CPU core
Data encryption and decryption for memories (Flash/SRAM)
Supports Secure Memory Protection Unit ( SMPU ) for Flash and RAM
System Clock: 4.5/9/18/36 MHz (default)
CPU operating frequency: Max. 34 MHz, Typical 17 MHz
Crypto Engine operating frequency : up to 34 MHz
Operating power supply voltage: 1.62V - 5.5V
Operating temperature: -25°C to 85°C
ESD protection up to 4000V
Memory
FLASHROM
576(2*288) Kbytes Flash ROM as data/program memory
Software commands for data protection (SDP)
Support the unique ID of each chip
Data retention: at least 10 years
RAM
32 Kbytes auxiliary SRAM
Crypto Co-processor
True random number generator (TRNG)
Physical unclonable function (PUF)
Triple-DES accelerator
Advanced Encryption Standard (AES) accelerator
Support 128, 192 & 256 bits key mode
PKC (Public-Key Coprocessors)
2048 bits maximum key length for RSA with randomly modulus (32 bits per step configurable)
Mathematical Library to support ECC Curve (P-Curve) up to 521 bits
SHA accelerator
Support SHA-1 & SHA-256 mode
Interface
ISO 7816
Three smart control of serial interface for ISO-7816 specification
ISO 7816-3 compliant electrical interface and response T=0 and T=1 protocol
Contact configuration and serial interface according to ISO/IEC 7816: GND, VCC, CLK, RST and IO
Single-Wire Protocol
SPI
UART Supported
I2C
Security Circuits
High/low voltage detector
High/low frequency detector
High/low temperature detector
Light sensors
Security reset detection
Special hardware for protection against SPA/DPA attacks
Auto self-test for security circuits right after chip reset
Active shield against physical probing
Supported Standards
ISO/IEC 7816
GSM 11.11, 11.12
ETSI 102 613 V9.1.0
Supported SM2, SM3 and SM4 Cryptography Algorithms


安全芯片规格 32-bits Andes SN801 Secure CPU core Data encryption and decryption for memories (Flash/SRAM) Supports Secure Memory Protection Unit ( SMPU ) for Flash and RAM System Clock: 4.5/9/18/36 MHz (default) CPU operating frequency: Max. 34 MHz, Typical 17 MHz Crypto Engine operating frequency : up to 34 MHz Operating power supply voltage: 1.62V - 5.5V Operating temperature: -25°C to 85°C ESD protection up to 4000V Memory FLASHROM 576(2*288) Kbytes Flash ROM as data/program memory Software commands for data protection (SDP) Support the unique ID of each chip Data retention: at least 10 years RAM 32 Kbytes auxiliary SRAM Crypto Co-processor True random number generator (TRNG) Physical unclonable function (PUF) Triple-DES accelerator Advanced Encryption Standard (AES) accelerator Support 128, 192 & 256 bits key mode PKC (Public-Key Coprocessors) 2048 bits maximum key length for RSA with randomly modulus (32 bits per step configurable) Mathematical Library to support ECC Curve (P-Curve) up to 521 bits SHA accelerator Support SHA-1 & SHA-256 mode Interface ISO 7816 Three smart control of serial interface for ISO-7816 specification ISO 7816-3 compliant electrical interface and response T=0 and T=1 protocol Contact configuration and serial interface according to ISO/IEC 7816: GND, VCC, CLK, RST and IO Single-Wire Protocol SPI UART Supported I2C Security Circuits High/low voltage detector High/low frequency detector High/low temperature detector Light sensors Security reset detection Special hardware for protection against SPA/DPA attacks Auto self-test for security circuits right after chip reset Active shield against physical probing Supported Standards ISO/IEC 7816 GSM 11.11, 11.12 ETSI 102 613 V9.1.0 Supported SM2, SM3 and SM4 Cryptography Algorithms
音频芯片规格 8-bit turbo 8051 CPU core(average 9 times faster than standard 12 clock mode 8051) 12MHz on-chip oscillator, no external clock source is needed 24K bytes of MTP (Multiple Times Programming) memory for program code storage USB 2.0 full-speed for HID and UAC2.0 Hi-Definition (96KHz sampling) Audio Digital to Analog Converter (DAC) Hi-Quality (48KHz sampling) Analog to Digital Converter (ADC) capacitor-less headphone drivers with a smart headphone detector for real-time headphone plug-in detection, headphone type (OMTP/CTIA) detection, and remote control detection of Apple EarPods and Android-defined earpieces. Ra/Rd resistors for PD3.0 protocol setting purpose PD3.0 SOP’ communication state machine GPIOs/PWMs I2S/I2C/UART interfaces two-wire serial bus for loading program memory purpose